184PIN DDR333 Unbuffered DIMM

128MB With 16Mx16 CL2.5

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1 CKEn /CS /RAS /CAS /WE BA

0,1

/AP A

11,

Note

Extended

Mode Register Set

H X L L L L OP CODE 1,2

Auto Refresh H 3

Entry

LL L H X

L H H H 3

Refresh

Self

Refresh

Exit L H

H X X X

Bank Active & Row Addr. H X L L H H V Row Address

Auto Precharge Disable L 4

Read &

Column Address

Auto Precharge Enable

H X L H L H V

Column

Address

)

Auto Precharge Disable L 4

Write &

Column Address

Auto Precharge Enable

H X L H L L V

Column

Address

)

4, 6

Burst Stop H X L H H L X 7

Bank Selection V L

Precharge

All Banks

H X L L H L

X H

H X X X

Entry H L

L V V V

Active Power Down

Exit L H X X X X

H X X X

Entry

H L

L H H H

H X X X

Precharge Power

Down Mode

Exit

L H

L V V V

DM H X X 8

H X X X 9

No Operation Command

H X

L H H H

Note: 1. OP Code: Operand Code. A0 ~ A12 & BA0 ~ BA1: Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM. The automatically precharge without row precharge command is meant by

"Auto". Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1: Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both

BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at

read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D

is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after

the end of burst. New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in is masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation (NOP)" in DDR SDRAM.

Transcend Information Inc.

1 2 ... 5 6 7 8 9 10 11 12

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