Transcend TS4GHR72V1C Ficha Técnica

Consulte online ou descarregue Ficha Técnica para Módulos de memória Transcend TS4GHR72V1C. Transcend Transcend TS4GHR72V1C memory module Manual do Utilizador

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DDR4
TS1GHR72V1Z
TS2GHR72V1Z
288Pin DDR4 2133 RDIMM
8GB~16GB Based on 1Gx4
Description
DDR4 Registered DIMM is high-speed, low power
memory module that use 1Gx4bits DDR4 SDRAM in
FBGA package and a 4Kbits serial EEPROM on a
288-pin printed circuit board. DDR4 Registered DIMM is a
Dual In-Line Memory Module and is intended for
mounting into 288-pin edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
RoHS compliant products.
JEDEC standard 1.2V ± 0.06V power supply
VDDQ=1.2V ± 0.06V
Clock Freq: 1067MHZ for 2133Mb/s/Pin.
Programmable CAS Latency: 10,11,12,13,14,15,16
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
Programmable /CAS Write Latency (CWL)
= 11, 14(DDR4-2133)
8 bit pre-fetch
Burst Length: 4, 8
Bi-directional Differential Data-Strobe
On Die Termination with ODT pin
Serial presence detect with EEPROM
On DIMM Thermal Sensor
Pin Identification
Symbol
Function
A0~A15
Register address input
BA0, BA1
Register bank select input
BG0, BG1
Register bank group select input
RAS_n
Register row address strobe input
CAS_n
Register column address strobe
input
WE_n
Register write enable input
CS0_n, CS1_n,
CS2_n, CS3_n
DIMM Rank Select Lines input
CKE0, CKE1
Register clock enable lines input
ODT0, ODT1
Register on-die termination control
lines input
ACT_n
Register input for activate input
DQ0~Q63
DIMM memory data bus
CB0~B7
DIMM ECC check bits
TDQS9_t~TDQS17_t
TDQS9_c~TDQS17_c
Dummy loads for mixed populations
of x4 based and x8 based RDIMMs.
DQS0_t~DQS17_t
Data Buffer data strobes
(positive line of differential pair)
DQS0_c~DQS17_c
Data Buffer data strobes
(negative line of differential pair)
CK0_t, CK1_t
Register clock input (positive line of
differential pair)
CK0_c, CK1_c
Register clocks input (negative line
of differential pair)
SCL
I2C serial bus clock for SPD/TS
and register
SDA
I2C serial bus data line for SPD/TS
and register
SA0~SA2
I2C slave address select for
SPD/TS and register
PAR
Register parity input
VDD
SDRAM core power supply
VREFCA
SDRAM command/address
reference supply
VSS
Power supply return (ground)
VDDSPD
Serial SPD/TS positive power
supply
ALERT_n
Register ALERT_n output
VPP
SDRAM activating power supply
RESET_n
Set Register and SDRAMs to a
Known State
EVENT_n
SPD signals a thermal event has
occurred.
VTT
SDRAM I/O termination supply
RFU
Reserved for future use
NC
No Connection
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Resumo do Conteúdo

Página 1

DDR4 TS1GHR72V1Z TS2GHR72V1Z 288Pin DDR4 2133 RDIMM 8GB~16GB Based on 1Gx4 Description DDR4 Registered DIMM is high-speed, low power memo

Página 2

16GB, 2Gx72 Module(2 Rank x4) Parameter Symbol DDR4 2133 CL15 Unit Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),

Página 3

Timing Parameters & Specifications Speed DDR4 2133 Unit Parameter Symbol Min Max Average Clock Period tCK 0.938 <1.071 ns CK high-leve

Página 4

WRITE recovery time tWR 15 - ns Mode Register Set command cycle time tMRD 8 - nCK Speed DDR4 2133 Unit Parameter Symbol Min Max CAS_n to CAS_n

Página 5

SERIAL PRESENCE DETECT SPECIFICATION TS1GHR72V1Z Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 Numb

Página 6

same bank group 41-59 Reserved - 00 60-77 Connector to SDRAM Bit Mapping - - 78-116 Reserved - 00 117 Fine Offset for Minimum CAS to CAS Delay T

Página 7

384-551 End User Programmable - - TS2GHR72V1Z Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 Number of

Página 8

60-77 Connector to SDRAM Bit Mapping - - 78-116 Reserved - 00 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group - 8

Página 9

DDR4 TS2GHR72V1PL 288Pin DDR4 2133 VLP RDIMM 16GB Based on 2Gx4 DDP Description DDR4 VLP Registered DIMM is high-speed, low power memo

Página 10

EVENT_n SPD signals a thermal event has occurred. VTT SDRAM I/O termination supply RFU Reserved for future use NC No Connection Dimensions (Uni

Página 11

Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.

Página 12

Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.

Página 13

Pin Assignments Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name

Página 14

Block Diagram 16GB, 2Gx72 Module(2 Rank x4) This technical information is based on industry standard

Página 15

Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 85 ℃ 1,2 Note: 3. Operating Temperature is t

Página 16

Differential AC and DC Input Levels Parameter Symbol DDR4-1600/1866/2133 Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3

Página 17

IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 16GB, 2Gx72 Module(2 Rank x4) Par

Página 18

Timing Parameters & Specifications Speed DDR4 2133 Unit Parameter Symbol Min Max Average Clock Period tCK 0.938 <1.071 ns CK high-level

Página 19

Speed DDR4 2133 Unit Parameter Symbol Min Max CAS_n to CAS_n command delay for same bank group tCCD_L 6 - nCK CAS_n to CAS_n command d

Página 20

SERIAL PRESENCE DETECT SPECIFICATION TS2GHR72V1PL Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 Number

Página 21

78-116 Reserved - 00 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group - 83 118 Fine Offset for Minimum Activate to

Página 22 - DDQ pin relative to Vss

Pin Assignments Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name

Página 23

Block Diagram 8GB, 1Gx72 Module(1 Rank x4)

Página 24

Block Diagram 16GB, 2Gx72 Module(2 Rank x4)

Página 25

This technical information is based on industry standard data and tests believed to be relia

Página 26

Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 85 ℃ 1,2 Note: 1. Operating Temperature is t

Página 27

Differential AC and DC Input Levels Parameter Symbol DDR4-1600/1866/2133 Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3

Página 28

IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 8GB, 1Gx72 Module(1 Rank x4) Para

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