Transcend TS4GHR72V1C Ficha Técnica descarregar pdf (Página 16)

60-77

Connector to SDRAM Bit Mapping

78-116

Reserved

117

Fine Offset for Minimum CAS to CAS Delay Time

(tCCD_Lmin), same bank group

118

Fine Offset for Minimum Activate to Activate Delay

Time (tRRD_Lmin), same bank group

119

Fine Offset for Minimum Activate to Activate Delay

Time (tRRD_Smin), different bank group

120

Fine Offset for Minimum Active to Active/Refresh

Delay Time (tRCmin)

121

Fine Offset for Minimum Row Precharge Delay Time

(tRPmin)

122

Fine Offset for Minimum RAS to CAS Delay Time

(tRCDmin)

123

Fine Offset for Minimum CAS Latency Time (tAAmin)

124

Fine Offset for SDRAM Maximum Cycle Time

(tCKAVGmax)

125

Fine Offset for SDRAM Minimum Cycle Time

(tCKAVGmin)

126-127

Cyclical Redundancy Code

128

Raw Card Extension, Module Nominal Height

31.25mm

129

Module Maximum Thickness

Planar Double Sides

130

Reference Raw Card Used

Revision 0, Raw card A

131

DIMM Module Attributes

2 Row,1 Register

132

RDIMM Thermal Heat Spreader Solution

Not incorporated

133-134

By Manufacturer

Variable

135

By Manufacturer

Variable

136

Address Mapping from Register to DRAM

Mirrored

137

Moderate Drive:

Chip select, ODT, CKE

Strong Drive:

Command/Address

138

Moderate Drive

139-253

Reserved

254-255

Cyclical Redundancy Code (CRC)

256-319

Reserved

320-321

Module Manufacturer ID Code

322

Module Manufacturing Location

323-324

Module Manufacturing Date

325-328

Module Serial Number

329-348

Module Part Number

349

Module Revision Code

350-351

DRAM Manufacturer ID Code

By Manufacturer

Variable

352

DRAM Stepping

353-381

Manufacturer Specific Data

By Manufacturer

Variable

382-383

Reserved

384-551

End User Programmable

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 27 28

DD relative to Vss 22
DDQ pin relative to Vss 22

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Transcend TS4GHR72V1C Ficha Técnica Página 16

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